The present invention relates to a semiconductor integrated circuit. Semiconductor integrated circuits according to the present invention can be effectively applied to memories, electronic control units, and processor units that have such-semiconductor integrated circuits as components.
A method of forming a MOS field effect transistor (hereinafter abbreviated to MOS) in a single crystalline semiconductor layer on an insulator is known as an SOI (Silicon On Insulator) MOS structure (hereinafter abbreviated to SOIxc2x7MOS) forming method. The MOS has a thick insulator directly thereunder, and therefore is characterized by its ability to reduce drain junction capacitance and signal line to substrate capacitance to about {fraction (1/10)} of those of conventional MOS. In addition, the MOS is insulated and separated from its supporting substrate, and therefore is also characterized by its ability to substantially eliminate drawback due to irradiation with xcex1 rays and latch up phenomena.
Also, as a technique for utilizing the characteristic of SOIxc2x7MOS regions of being insulated and separated from each other, there is a method of allowing threshold voltage of SOIxc2x7MOS to vary depending on applied gate voltage by electrically connecting a substrate and a gate electrode of the SOIxc2x7MOS with each other. This method is proposed in 1994 International Electron Devices Meeting papers p.809 under the title xe2x80x9cA dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation.xe2x80x9d An example of a structure formed by this method is shown in an equivalent circuit diagram of FIG. 2(a) and a plan arrangement view of FIG. 3. According to the above method, a substrate 3 of SOIxc2x7MOS is connected to a gate electrode 6 outside of a channel region by a metallic interconnection 61 via connection holes 112 and 113. Therefore, body potential rises with increase in applied gate voltage. This results in a forward direction current between a source and a drain, and therefore properties of the transistor exhibit a punch through state, thus resulting in an increase in the current value. In n-channel SOIxc2x7MOS, such a state corresponds to a state in which a threshold voltage value is turned negative. When the applied gate voltage is lowered, the body potential decreases. Therefore, the threshold voltage value is turned positive, thus resulting in a decrease in the current value. According to the structure described above, in which the body potential is controlled so as to vary with gate potential, it is possible to achieve properties such that the gradient of dependence of source-drain current on gate voltage is smaller than a gradient value of conventional SOIxc2x7MOS. Thus, the structure as described above is characterized by a great current obtained even at a lower supplied voltage than that of a conventional structure.
For the purpose of solving problems with the structure shown in FIG. 2(a), there is proposed a method of inserting a diode between the gate and the substrate. The method is illustrated in FIG. 2(b).
The conventional methods illustrated in FIGS. 2(a) and 2(b) make use of a structure specific to SOIxc2x7MOS, in which its body region is completely isolated from the outside, in order to achieve lower operating voltage by controlling the body potential by some method or another. In the case of the structure with its body region completely isolated from the outside, so-called floating body effect is known as the greatest problem with the SOIxc2x7MOS. The floating body effect refers to the following phenomena. Minority carriers generated by a strong drain electric field are accumulated in the body because the minority carriers have no path to flow out of the body region. The carriers accumulated in the body cause variations in threshold voltage and also cause abnormal hump properties to appear in current-voltage properties.
According to the above-mentioned method, the body potential is fixed to the gate potential, and therefore the problems of floating body effect are also solved.
In the case of a semiconductor integrated circuit formed on a normal Si substrate, there is also a conceivable system in which well potential is made variable by using a control circuit, so that the threshold voltage value of a transistor in a well region is made variable. According to this system, the threshold voltage values of all transistors in the well region are changed in the same manner.
A first object of the present invention is to provide SOIxc2x7MOS that has variable threshold voltage properties and enables lower voltage operation while ensuring high speed operation.
A second object of the present invention is to solve various problems caused by floating body effect. The various problems caused by floating body effect are the greatest disadvantage of a semiconductor device using an SOI substrate. Specific examples of the problems caused by floating body effect are variations in threshold voltage, appearance of abnormal hump properties in current-voltage properties, and a decrease in source-drain breakdown voltage.
A third object of the present invention is to not only solve the above-mentioned problems but also ensure high density circuit integration.
A fourth object of the present invention is to provide a fabrication method in which the above-mentioned problems are solved by a simpler method.
Background of the objects will hereinafter be described.
The DTMOS mentioned above has a problem in that it is not suitable for greater current and higher speed operation. FIG. 2(a) shows an inverter structure formed by DTMOS techniques. In this structure, application of gate voltage results in a forward direction between a source and a substrate, thereby causing a fatal defect in that a current flows from a gate to the source. In addition, because of the forward direction between the source and the substrate, the gate voltage cannot essentially be raised beyond built-in potential (about 0.6 V) of a source junction. Therefore, when the structure is operated at a supplied voltage of more than 0.6 V, the driving current of the structure becomes lower, rather than greater, than that of a normal structure MOS. Thus, from viewpoints of higher current and higher speed operation, improvements in properties of the structure cannot be expected. This means that the structure will only waste power at a supplied voltage of more than 0.6 V.
FIG. 2(b) shows an example of an inverter in which consideration is given to measures to solve the problems of the DTMOS. In this example, it is possible to apply a gate voltage higher than the built-in potential of a source junction because of the presence of reverse-biased diodes. However, with this system, no effects can be expected from a viewpoint of eliminating floating body effect, which is known as the greatest problem of SOIxc2x7MOS. With this structure, it is not possible to extract carriers generated in the body by a strong drain electric field. This means that in the case of n-channel MOS, holes are accumulated in the body, whereas in the case of p-channel MOS, electrons are accumulated. The accumulated carriers cannot be extracted in a connection path to a gate because of the presence of the reverse-biased diodes. Thus, with this structure, it is not possible to solve problems specific to floating body effect such as variations in threshold voltage, decrease in breakdown voltage, and instability in high-frequency operation.
Moreover, the inverter structure shown in FIG. 2(b) has another problem. Specifically, this structure involves complication of circuit design and increase in occupied area, because the structure requires a new periphery circuit for control of transistors MP1 and MP2. When compared with a normal SOIxc2x7MOS, the DTMOS structure shown in FIG. 2(a) also has a problem of an additional occupied area for substrate to gate connection outside its channel region. However, the structure of FIG. 2(b) further increases its occupied area, and therefore has a disadvantage of more significantly lowering the degree of integration of an integrated circuit.
As another system for rendering threshold voltage variable, a well potential variable method is conceivable. This well potential variable method can be expected to be effective in achieving higher speed operation and lower power consumption as compared with a method in which well potential is not variable. However, with this method, it is not possible to effect individual control of threshold voltage of each transistor. The method has a disadvantage of being unable to reduce leakage current in some transistor sections disposed in a well even in a condition where, for example, the threshold voltage of the transistors is to be maintained at a high value and leakage current is to be reduced. This is because the threshold voltages of all transistors in the well are changed in the same manner. Thus, it is not possible to effect individual control of threshold voltage of each transistor. In order to solve the above problem, it is necessary to perform well isolation for each transistor and provide a well potential control circuit for each isolated well. However, this presents a problem that will hinder higher circuit integration. Another disadvantage with the well potential control method is that well to substrate capacitance is relatively large, and therefore it is difficult to control well potential at super high speed.
It is accordingly an object of the present invention to solve, in principle, the problem with the conventional structures shown in FIGS. 2(a) and 2(b), that is, the problem with the structures that have gate voltage-dependent variable threshold voltage properties but have a fatal shortening in that gate current flows into the source. According to the present invention, it is possible to provide SOIxc2x7MOS that has variable threshold voltage properties and enables low voltage operation.
It is another object of the present invention to provide SOIxc2x7MOS in which no limit is set on applied gate voltage conditions, and therefore a gate voltage higher than source built-in potential can be applied, and thus to provide a low power consumption semiconductor integrated circuit that can achieve higher driving current and super high speed operation even at a usual supplied voltage of more than 0.6 V.
A further object of the present invention is to solve the problem with the method of rendering threshold voltage variable for each well unit. According to the present invention, it is possible to raise the threshold voltages of all transistors in a non-conducting state and lower the threshold voltages in a conducting state. In addition, according to the present invention, it is possible to provide a super high speed and low power consumption integrated circuit suitable for higher circuit integration.
A further object of the present invention is to enable higher circuit integration. For example, the conventional structure shown in FIG. 2(a) requires an additional area for substrate to gate electrode connection. The conventional structure shown in FIG. 2(b) makes higher circuit integration more difficult than the structure of FIG. 2(b), because diodes and their control circuits are added.
A further object of the present invention is to provide an inexpensive semiconductor device to which a conventional circuit can be applied as it is, without the need for designing an additional control circuit for variable threshold voltage properties.
A further object of the present invention is to provide a semiconductor device of new structure in which floating body effect of SOIxc2x7MOS is eliminated by a simple fabrication method.
A further object of the present invention is to provide a method in which floating body effect of SOIxc2x7MOS can be completely eliminated only by conventional fabrication techniques, that is, inexpensive fabrication techniques without the need for developing new fabrication techniques.
An essential concept of the present invention is to set a single transistor to be a fundamental unit with a variable threshold voltage, and enable low power and super high speed operation without any need for essential modification to conventional circuit design methods. Therefore, in the present invention, it is desirable to use an SOI substrate, which is most suitable for isolating device substrates of transistors from each other.
Next, main aspects of the present invention disclosed in the present specification will be briefly described.
In the present specification, as relating to substrates, terms xe2x80x9cdevice substratexe2x80x9d and xe2x80x9csupporting substratexe2x80x9d are used. The xe2x80x9cdevice substratexe2x80x9d refers to a semiconductor substrate on which a single unit semiconductor device, which will be described below, is mounted. The xe2x80x9csupporting substratexe2x80x9d refers to a substrate supporting a semiconductor integrated circuit that comprises single unit semiconductor devices and has a specific function. In general, device substrates are mounted on a supporting substrate, whereby a semiconductor device is formed.
In aspects of the present invention described in the following (1) to (5), fundamental aspects of forming a single unit semiconductor device by using a plurality of semiconductor members are illustrated. By using xe2x80x9csingle unit semiconductor devices,xe2x80x9d various semiconductor integrated circuits having specific functions such as logic circuits and memories are formed.
(1) According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a first MOS field effect transistor of a first conduction type and a second MOS field effect transistor of the first conduction type which form a single unit semiconductor device; and a device substrate mounted with the single unit semiconductor device and isolated from other semiconductor devices; wherein a circuit configuration is formed by a semiconductor device group including at least the single unit semiconductor device, the second MOS field effect transistor including a gate electrode connected to a gate electrode of the first MOS field effect transistor; a drain connected to a drain of the first MOS field effect transistor; and a source connected both to a device substrate of the first MOSFET and a source of the first MOS field effect transistor via a resistor and a device substrate of the first MOS field effect transistor.
The single unit semiconductor device in this example is shown in FIG. 1(a).
(2) According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising a MOS field effect transistor and a capacitor which form a single unit semiconductor device; and a device substrate mounted with the single unit semiconductor device and isolated from other semiconductor devices; wherein a circuit configuration is formed by a semiconductor device group including at least the single unit semiconductor device, the capacitor including one electrode connected to a gate electrode of the MOS field effect transistor; and another electrode connected to a source of the MOS field effect transistor via a resistor and a device substrate of the MOS field effect transistor.
The single unit semiconductor device in this example is shown in FIG. 12(a).
(3) According to a third aspect of the present invention, there is provided a semiconductor integrated circuit comprising a first MOS field effect transistor of a first conduction type, a second MOS field effect transistor of the first conduction type, and a third MOS field effect transistor of a second conduction type which form a single unit semiconductor device; and a device substrate mounted with the single unit semiconductor device and isolated from other semiconductor devices; wherein a circuit configuration is formed by a semiconductor device group including at least the single unit semiconductor device, the second MOS field effect transistor including a gate electrode connected to a gate electrode of the first MOS field effect transistor; and a drain connected to a device substrate of the first MOS field effect transistor; and the third MOS field effect transistor including a gate electrode connected to a gate electrode of the second MOS field effect transistor; a drain connected to a device substrate of the first MOS field effect transistor; and a source connected to a source of the first MOS field effect transistor.
The single unit semiconductor device in this example is shown in FIG. 18(a).
(4) According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit according to the third aspect, wherein the third MOS field effect transistor is of the first conduction type; and the gate electrode of the third transistor is connected to a drain of the first MOS field effect transistor.
(5) According to fifth to eighth aspects of the present invention, there is provided a semiconductor integrated circuit according to the first to fourth aspects, wherein the semiconductor device is isolated from a supporting substrate of the semiconductor integrated circuit by an insulator, and is isolated from another semiconductor device by an insulator.
The following aspects (6) to (10) of the present invention will describe forms of CMOS.
(6) According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a supporting substrate having at least a first substrate region and a second substrate region electrically isolated from each other; a first MOS field effect transistor and a second MOS field effect transistor which form the first substrate region; and a third MOS field effect transistor and a fourth MOS field effect transistor which form the second substrate region; wherein a single unit semiconductor device is formed by at least the first to fourth MOS field effect transistors; and a circuit configuration is formed by a semiconductor device group including at least the single unit semiconductor device, the second MOS field effect transistor including a gate electrode connected to a gate electrode of the first MOS field effect transistor; a drain connected to a drain of the first MOS field effect transistor; and a source connected to a source of the first MOS field effect transistor via a first resistor and a device substrate of the first MOS field effect transistor; and the fourth MOS field effect transistor including a gate electrode connected to a gate electrode of the third MOS field effect transistor; a drain connected to a drain of the third MOS field effect transistor; and a source connected to a source of the third MOS field effect transistor via a second resistor and a device substrate of the third MOS field effect transistor.
This example is shown in FIG. 1(b).
(7) According to a tenth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a supporting substrate having at least a first substrate region and a second substrate region electrically isolated from each other; a first MOS field effect transistor of a first conduction type and a first capacitor which form the first substrate region; and a second MOS field effect transistor of a second conduction type and a second capacitor which form the second substrate region; wherein a single unit semiconductor device is formed by at least the first and second MOS field effect transistors and the first and second capacitors; and a circuit configuration is formed by a semiconductor device group including at least the single unit semiconductor device, the first capacitor including one electrode connected to a gate electrode of the first MOS field effect transistor; and another electrode connected to a source of the first MOS field effect transistor via a first resistor and a device substrate of the first MOS field effect transistor; and the second capacitor including one electrode connected to a gate electrode of the second MOS field effect transistor; and another electrode connected to a source of the first MOS field effect transistor via a second resistor and a device substrate of the first MOS field effect transistor.
This example is shown in FIG. 12(b).
(8) According to an eleventh aspect of the present invention, there is provided a semiconductor integrated circuit comprising a supporting substrate having at least a first substrate region and a second substrate region electrically isolated from each other; a first MOS field effect transistor of a first conduction type, a second MOS field effect transistor of the first conduction type, and a third MOS field effect transistor of a second conduction type which form the first substrate region; and a fourth MOS field effect transistor of the second conduction type, a fifth MOS field effect transistor of the second conduction type, and a sixth MOS field effect transistor of the first conduction type which form the second substrate region; wherein a single unit semiconductor device is formed by at least the first to sixth MOS field effect transistors; and a circuit configuration is formed by a semiconductor device group including at least the single unit semiconductor device, the second MOS field effect transistor including a gate electrode connected to a gate electrode of the first MOS field effect transistor; a drain connected to a drain of the first MOS field effect transistor; and a source connected to a device substrate of the first MOS field effect transistor, the second MOS field effect transistor sharing a device substrate with the first MOS field effect transistor; the fourth MOS field effect transistor including a gate electrode connected to a gate electrode of the first MOS field effect transistor; and a drain connected to a drain of the first MOS field effect transistor; and the fifth MOS field effect transistor including a gate electrode connected to a gate electrode of the first MOS field effect transistor; a drain connected to a device substrate of the fourth MOS field effect transistor; and a source connected to a source of the fourth MOS field effect transistor.
This example is shown in FIG. 18(b).
(9) According to a twelfth aspect of the present invention, there is provided a semiconductor integrated circuit according to the eleventh aspect, wherein the third MOS field effect transistor is of the first conduction type and has a gate electrode connected to the drain of the first transistor; and the sixth MOS field effect transistor is of the second conduction type and has a gate electrode connected to the drain of the first transistor.
(10) According to thirteenth to sixteenth aspects of the present invention, there is provided a semiconductor integrated circuit according to the ninth to twelfth aspects, wherein the semiconductor device is isolated from the supporting substrate of the semiconductor integrated circuit by an insulator, and is isolated from another semiconductor device by an insulator.
Applications of the present invention to NAND or NOR circuits will be illustrated in the following.
(11) According to a seventeenth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a plurality of sets of first MOS field effect transistors of a first conduction type and second MOS field effect transistors of the first conduction type which correspond to a plurality of input nodes, one of the first MOS field effect transistors and one of the second MOS field effect transistors together forming one set and having gate electrodes connected to one input node; wherein a group of the first transistors in the sets of the transistors share a body node to form a first series connection; and a group of the second transistors in the sets of the transistors share a body node to form a second series connection, one end of each of the first and second series connections being connected to an output node, another end of the first series connection being connected to a power supply node, and another end of the second series connection being connected to the body node and the power supply node via a resistor, whereby a portion of a NAND type gate circuit or a NOR type gate circuit is formed.
(12) According to an eighteenth aspect of the present invention, there is provided a semiconductor integrated circuit according to the second aspect or the sixth aspect, wherein a plurality of semiconductor devices are connected in series with each other to form a series connection, one end of the series connection being connected to an output node and another end of the series connection being connected to a power supply node, whereby a portion of a NAND type gate circuit or a NOR type gate circuit is formed.
(13) According to a nineteenth aspect of the present invention, there is provided a semiconductor integrated circuit according to the seventeenth aspect, wherein the resistor is replaced with a third MOS field effect transistor of a second conduction type, and a gate electrode of the third transistor is connected to one input node.
(14) According to a twentieth aspect of the present invention, there is provided a semiconductor integrated circuit according to the nineteenth aspect, wherein the third transistor is replaced with a third TMOS field effect transistor of a first conduction type, and a gate electrode of the third MOS field effect transistor is connected to an output node.
(15) According to a twenty-first aspect of the present invention, there is provided a semiconductor integrated circuit according to the seventeenth aspect, wherein the resistor and a plurality of the groups of the transistors sharing device substrate nodes to form series connections are isolated from a supporting substrate of the semiconductor integrated circuit by an insulator, and are isolated by an insulator from another semiconductor device which does not share the device substrate nodes.
(16) According to twenty-second to twenty-fourth aspects of the present invention, there is provided a semiconductor integrated circuit according to the eighteenth to twentieth aspects, wherein the semiconductor devices are isolated from a supporting substrate of the semiconductor integrated circuit by an insulator, and are isolated from each other by an insulator.
(17) According to a twenty-fifth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a first MOS field effect transistor; and a second MOS field effect transistor and a third MOS field effect transistor each having a gate electrode connected to a gate electrode of the first MOS field effect transistor, the second transistor including a source and a drain connected to a source and a body node of the first transistor, respectively, and the third transistor including a source and a drain connected to the body node and a drain of the first transistor, respectively.
(18) According to a twenty-sixth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a first MOS field effect transistor of a first conduction type; and a second transistor and a third transistor each of a second conduction type and respectively controlled by a source and a drain of the first MOS field effect transistor, the second transistor including a source connected to the source of the first transistor via a first resistor; and a drain connected to a body node of the first transistor; and the third transistor including a source connected to the body node of the first transistor; and a drain connected to the drain of the first transistor via a second resistor.
(19) According to a twenty-seventh aspect of the present invention, there is provided a semiconductor integrated circuit according to the twenty-sixth aspect, wherein a capacitor is added between a gate electrode and the body node of the first transistor.
(20) According to a twenty-eighth aspect of the present invention, there is provided a semiconductor integrated circuit according to the preceding aspects, wherein the resistor is formed in a semiconductor thin film.
(21) According to a twenty-ninth aspect of the present invention, there is provided a semiconductor integrated circuit according to the preceding aspects, wherein the resistor is formed in a single crystalline semiconductor layer in which a transistor is formed.
(22) According to a thirtieth aspect of the present invention, there is provided a semiconductor integrated circuit according to the preceding aspects, wherein the resistor has a resistance value of 500 kxcexa9 or less and 1 kxcexa9 or more.
(23) According to a thirty-first aspect of the present invention, there is provided a semiconductor integrated circuit according to the first, fifth, seventeenth, and twenty-first aspects, wherein an absolute value of threshold voltage of the second transistor is set lower than an absolute value of threshold voltage of the first transistor.
(24) According to a thirty-second aspect of the present invention, there is provided a semiconductor integrated circuit according to the third, fourth, seventh, eighth, nineteenth, twentieth, and twenty-third to twenty-fifth aspects, wherein absolute values of threshold voltages of the second transistor and the third transistor are set lower than an absolute value of threshold voltage of the first transistor.
(25) According to a thirty-third aspect of the present invention, there is provided a semiconductor integrated circuit according to the ninth and thirteenth aspects, wherein absolute values of threshold voltages of the second transistor and the fourth transistor are set lower than absolute values of threshold voltages of the first transistor and the third transistor.
(26) According to a thirty-fourth aspect of the present invention, there is provided a semiconductor integrated circuit according to the eleventh, twelfth, fifteenth, and sixteenth aspects, wherein absolute values of threshold voltages of the second transistor, the third transistor, the fifth transistor, and the sixth transistor are set lower than absolute values of threshold voltages of the first transistor and the fourth transistor.
(27) According to a thirty-fifth aspect of the present invention, there is provided a semiconductor integrated circuit according to the first, fifth, seventeenth, and twenty-first aspects, wherein channel width of the second transistor is ⅕ or less of channel width of the first transistor.
(28) According to a thirty-sixth aspect of the present invention, there is provided a semiconductor integrated circuit according to the third, fourth, seventh, eighth, nineteenth, twentieth, and twenty-third to twenty-fifth aspects, wherein channel widths of the second transistor and the third transistor are ⅕ or less of channel width of the first transistor.
(29) According to a thirty-seventh aspect of the present invention, there is provided a semiconductor integrated circuit according to the ninth and thirteenth aspects, wherein channel widths of the second transistor and the fourth transistor are ⅕ or less of channel widths of the first transistor and the third transistor.
(30) According to a thirty-eighth aspect of the present invention, there is provided a semiconductor integrated circuit according to the eleventh, twelfth, fifteenth, and sixteenth aspects, wherein channel widths of the second transistor, the third transistor, the fifth transistor, and the sixth transistor are ⅕ or less of channel widths of the first transistor and the fourth transistor.
(31) According to a thirty-ninth aspect of the present invention, there is provided a semiconductor integrated circuit according to the twenty-ninth aspect, wherein the resistor is formed in a single crystalline semiconductor layer between source and drain junctions of a MOS field effect transistor and a buried insulator.
The following aspect of the present invention relates to a fabrication method.
(32) According to an aspect of the present invention, there is provided a fabrication method comprising the steps of forming a gate electrode on a principal surface of a single crystalline semiconductor layer of a first conduction type isolated from a supporting substrate by a thick insulator with a thin insulator intermediate between the gate electrode and the principal surface of the single crystalline semiconductor layer; forming a shallow diffusion layer of a second conduction type with the gate electrode serving as a mask; forming a deep source or drain diffusion layer of the second conduction type in a section of a region where the shallow diffusion layer is formed so as not to allow a bottom of a source or drain junction to reach the thick insulator; creating holes whose bottoms reach the thick insulator in a section of the single crystalline semiconductor layer where only the shallow diffusion layer is formed and in a section of the single crystalline semiconductor layer where the deep diffusion layer is formed; and forming conductive layers in the holes and thereby short-circuiting a region of the first conduction type and a region of the second conduction type.
The deep diffusion layer forms a source or a drain. In the present invention, it is important to form the deep diffusion layer so as not to allow the bottom of a junction formed by the deep diffusion layer to reach the thick insulator. A resistance RS formed at the bottom of the source diffusion layer plays a principal role in the present invention. By such a simple method, it is possible to form a structure in which a resistor is buried under the source diffusion layer.
Incidentally, the resistor (RS) may be provided externally of a semiconductor device according to the present invention. However, according to the method disclosed in the above aspect of the present invention, it is possible to form a buried structure by a simple method. This method is extremely useful as a fabrication method and from characteristic and practical points of view.
The following aspects (33) to (36) of the present invention will describe specific applications of semiconductor integrated circuits according to the present invention to various semiconductor devices, such as memories, transfer mode systems, and processor units.
(33) According to a forty-first aspect of the present invention, two pairs of semiconductor integrated circuits according to any of the ninth to sixteenth aspects form a single unit memory.
(34) According to a forty-second aspect of the present invention, there is provided a semiconductor integrated circuit according to any one of the twenty-fifth to twenty-seventh aspects, wherein one node of a MOS field effect transistor is connected with a capacitor, whereby a single unit memory is formed.
(35) According to a forty-third aspect of the present invention, a semiconductor integrated circuit according to any one of the first to thirty-eighth aspects forms an asynchronous transfer mode system.
(36) According to a forty-fourth aspect of the present invention, a semiconductor integrated circuit according to any one of the first to thirty-eighth aspects and a semiconductor integrated circuit according to any one of the first to thirty-fourth aspects form a processor unit.
(37) According to a forty-fifth aspect of the present invention, there is provided a semiconductor integrated circuit according to any one of the first, second, fifth, sixth, seventeenth, twenty-first, and twenty-sixth aspects, wherein the resistor is formed by a resistive functional device having linear or nonlinear properties, and a resistance value of the resistor is set higher than on resistance of a first transistor.
(38) According to a forty-sixth aspect of the present invention, there is provided a semiconductor integrated circuit according to any one of the ninth, tenth, thirteenth, and fourteenth aspects, wherein the resistor is formed by a resistive functional device having linear or nonlinear properties, and a resistance value of the resistor is set higher than on resistances of a first transistor and a third transistor.
(39) According to a forty-seventh aspect of the present invention, there is provided a semiconductor integrated circuit according to any one of the second, sixth, tenth, fourteenth, eighteenth, and twenty-second aspects, wherein a relation between source-drain current (IDS) of a transistor, a resistance value (RS) of a resistor, a capacitance value (CG) of a capacitor, and driven load capacitance (CL) is set such that a product of CG, RS, and ISD is equal to or greater than CL
(40) According to a forty-eighth aspect of the present invention, there is provided a semiconductor integrated circuit according to the forty-seventh aspect, wherein a product of CG and RS is equal to or greater than a reciprocal number of an operating frequency.
(41) Semiconductor integrated circuits according to the aspects of the present invention and other semiconductor integrated circuits can be connected in series, in parallel, or in series-parallel with each other and used in a desired manner according to the purpose. It is to be understood that in such a case, the semiconductor integrated circuits according to the aspects of the present invention retain their characteristics and effects.
[Operation Principles of Fundamental Structure of the Invention]
Operation principles of a fundamental structure of the present invention will be described. The fundamental structure is provided according to the foregoing first aspect of the present invention. In addition to explanation of the fundamental structure, an example of a complementary type semiconductor integrated circuit formed by using the fundamental structure will be described. These structures are mentioned in the foregoing sections (1) and (9).
The fundamental structure will be described with reference to a circuit diagram of FIG. 1(a). FIG. 1(a) is a circuit diagram of an n-channel MOS (abbreviated to nMOS). A control transistor M2 is inserted between a body node and a drain of a transistor M1 whose threshold voltage is to be made variable, and a resistor RS is inserted between the body node and a source of the transistor M1. A gate electrode of the transistor M2 is connected to a gate electrode of the transistor M1. Threshold voltage values of the transistors M1 and M2 are set to be positive values; however, it is desirable that the former be set at a normal value, and the latter be set at a value in the vicinity of 0 V. Channel width of the transistor M2 may be ⅕ or less, or preferably {fraction (1/10)} or less, of channel width of the transistor M1.
In the structure of FIG. 1(a), when a positive voltage is applied to the gate of the transistor M1 so as to bring the transistor M1 into a conducting state, the transistor M2 is also brought into a conducting state. In this case, body potential of M1 is obtained by dividing drain voltage by a resistance of the transistor M2 in a conducting state and the resistance RS. When the resistance RS is set higher than on resistance of the control transistor M2, or at a few kxcexa9 or higher, the body potential of M1 becomes substantially equal to the drain voltage. The increase in the body potential of M1 causes the threshold voltage of the transistor to change in a negative direction, thereby resulting in an increase in source-drain current.
When the drain voltage is more than 0.6 V, which is a built-in potential of the p-n junction, there occurs a new current path from the drain to a source diffusion layer in a forward-direction state via the body nodes of the transistors M2 and M1. However, this current does not have any adverse effects since the current flows only when the transistor M1 is in a conducting state and functions in such a manner as to further increase drain current. When a gate voltage is applied so as to bring the transistor M1 into a non-conducting state, the transistor M2 is also brought into a non-conducting state, and therefore the body node of M1 is cut off from an output node.
At this point, the resistor RS plays an important role in the present invention. Specifically, without the resistor RS, the non-conducting state of the transistor M2 causes a floating state in the body node of M1, and therefore various problems caused by floating body effect cannot be solved. By setting a resistance value of the resistor RS to a few Mxcexa9 or lower, body charge can be quickly extracted to the source node in a short time constant of picoseconds or less, thereby eliminating floating body effect. It is more desirable to set the resistance value of the resistor RS to 1 Mxcexa9 or lower.
[Prevention of Increase in Occupied Area and Fabrication Method]
It is not desirable from a viewpoint of higher circuit integration if arrangement of the resistor RS causes an increase in occupied area. In the present invention, the resistor RS is formed at the bottom of the source diffusion layer of the transistor M1 within the same SOI substrate that includes the transistors M1 and M2. This is intended to prevent an increase in occupied area and variations in properties due to difference in thermal coefficients.
Connection between the resistor RS and the M1 source node is realized by creating a hole also in the SOI layer in making a source connection hole so as to allow the hole to reach a buried insulator, filling the hole with an interconnection metal, and thereby short-circuiting the SOI substrate region and the source diffusion layer.
The resistance value of the resistor RS is determined by impurity concentration and thickness of a residual SOI region between the bottom of the source diffusion layer of M1 and the buried insulator, and width from an end of a source junction to an end of the source connection hole. Thus, junction depths of the source and drain diffusion layers need to be controlled precisely, and therefore attention should be directed to the following. There are so-called channeling phenomena in which at the time of ion implantation, impurities are aligned with a crystal lattice, and thus implanted deeper than a range determined by ion implantation energy. An abnormally extended low-concentration distribution resulting from the channeling phenomena poses a serious problem in controlling junction depth.
As methods for accurately forming a residual SOI region where the resistor RS is to be provided, (1) a tilt ion implantation method and (2) high-temperature treatment in a short time are employed in the present invention. Specifically, the tilt ion implantation method is carried out by setting a tilt angle of implantation for forming source and drain diffusion layers of the transistor M1 at 10 to 30 degrees with respect to a direction perpendicular to the single crystalline SOI layer. Activation of implanted ions through high-temperature treatment in a short time prevents not only abnormal spread of implanted ions resulting from channeling phenomena but also occurrence of transient enhance diffusion effect of implanted ions. By employing the tilt ion implantation method and the short-time high-temperature treatment, source and drain diffusion layers having a steep concentration distribution with a reduced low-concentration region are formed. Thus, it is possible to form a residual SOI layer of 10 nm or more at the bottom of a source diffusion layer in a well controlled manner.
In a symmetric source/drain structure, a resistance region as formed under the bottom of the source diffusion layer of the transistor M1 is similarly formed under the bottom of a drain diffusion layer. Since the resistance region is connected to a drain electrode via a drain connection hole, there is a fear of occurrence of a punch through path in which the substrate and the drain are short-circuited via the bottom portion of the drain diffusion layer irrespective of gate voltage. In order to prevent such a short circuit, impurity concentration, residual SOI thickness, and width of the bottom of the drain diffusion layer are set in such a manner that a substrate region at the bottom of the drain diffusion layer is completely depleted by application of drain voltage. In order to prevent occurrence of a punch through path at the bottom portion of the drain diffusion layer by using a drain depletion layer, the width of the bottom of the drain diffusion layer may be set at 100 nm or more under conditions of a applied drain voltage of 2 V, a residual SOI film thickness of 20 nm, and a substrate concentration of 1xc3x971017/cm3, for example. Under such conditions, drain leakage current can be controlled to 10xe2x88x9214 A/xcexcm or less, which is practically a negligible current value. Under the same conditions, by setting the width of the bottom of the source diffusion layer at 100 nm or more at a substrate potential of 0.5 V, it is possible at all times to realize a structure in which the resistor RS is buried under the bottom of the source diffusion layer.
It should be noted that the present invention is applicable to both nMOS and p-channel MOS (hereinafter abbreviated to pMOS). Also, there are conceivable modifications of the fundamental structure in which the transistor M2 is replaced with a capacitor, or the resistor RS is replaced with a transistor MN2, for example. Such modifications can also provide the same effects in terms of operating properties as described above. More specific description of the modifications will be made in a section of embodiments of the present invention.
[Application to Complementary Type Transistor]
FIG. 1(b) is an example of application of the present invention to a complementary type transistor (CMOS). In this example, the fundamental structure of the nMOS shown in FIG. 1(a) is also applied to pMOS by changing only the conduction type of the nMOS. With a circuit configuration of FIG. 1(b), it is possible to achieve low voltage and great current operation of pMOS without causing floating body phenomena by rendering its threshold voltage variable. Therefore, it is possible to realize SOIxc2x7CMOS capable of low voltage and high speed operation.
In an integrated circuit having the structure of the present invention, since threshold voltage of a transistor is made variable so as to follow change in gate voltage, its drain current rapidly rises even in a condition of low applied gate voltage, and therefore a significant effect of achieving greater current is obtained. In this example, as the gate voltage of the transistor is increased, its body potential also rises and the drain current increases without causing the problem of gate leakage current. The maximum drain current is generally defined by a current component obtained on the basis of punch through properties in the properties of the transistor, and an amount of increase in the absolute value of the current is limited.
For lower voltage operation, if the threshold voltage of a conventional transistor is set low, the same effect as described above can be obtained. A fundamental difference between the structure of the present invention and a conventional transistor with a low threshold voltage value is that the structure of the present invention can reduce leakage current to the same level attained by a conventional transistor with a high threshold voltage value.
The above-described method of eliminating the floating body effect of SOIxc2x7MOS according to the present invention can be realized only by combining conventional semiconductor fabrication methods, and therefore does not require development of new fabrication techniques. Therefore, according to the present invention, it is possible to provide a semiconductor device capable of low voltage and super high speed operation at low cost.